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Fermionic Design offers wide portfolio of PPA optimized SERDES IPs, wide-range PLLs and Analog-Glue IPs in various nodes. Fermionic Design IPs are highly programmable, developed using robust design flow and comes with after-sales integration support as well as documentation.

General purpose Frac-N synthesizers and special purpose PLLs (Zero-Delay-Buffers) and Clock-Distribution

Fermionic provides a configurable PLL-Core with ring or multi-gear LC VCO for clocking needs of SoC. Our PLL-core has been verified in a SERDES-applications.

 

Our PLLs product-line includes:

  • Fractional-N PLL core : Programmable, general purpose frequency synthesizers.​

  • Zero-Delay-Buffer PLL Cores for Multi-node Clock-distribution​

  • Compact low-area ring PLLs

  • General purpose core-supply programmable PLL-core

  • Multi-Phase PLL cores

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Deliverables

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GDSII, CDL Netlist
Verilog Model with loop dynamics
Liberty timing models (.lib)

LEF layout abstract

Application Note

User-guide

Integration support

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Fermionic SerDes PMA is silicon-proven in 28nm TSMC process


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  • Architecture Supports up to PCIe Gen5 (32Gbps) data-rate

  • Soft RTL for SERDES PIPE PCS

  • Supports multi-protocol USB4.0, PCIe Gen1/2/3/4/5, JESD204A/B/C

  • Integrated TX PLL

  • Programmable TX-FFE 

  • Architecture suitable for low-latency application

  • Programmable CTLE and adaptive 7-Tap DFE

  • Non-destructive Eye-monitor

  • PRBS Generator and checker

Analog General Purpose IPs


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  • Bandgap Reference

  • LDO, Power-management and supervisory control IPs

  • General Purpose ADC

  • CML buffers and multiplexers for low-jitter on-chip clock distribution

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